1. Field of The Invention
This invention relates to a memory storage system and more particularly to a memory storage system capable of operating in a reliable manner. More particularly the invention pertains to a method for forming a read only fusible link memory structure embodied in an integrated circuit structure including Field Effect Transistor cells whereby said read only memory is capable of directing utilization of redundant lines in place of defective memory array bits for information storage. The invention is further especially applicable to integrated memory circuit structures comprising field effect transistors serially connect to a capacitor, one plate of which is a current flow electrode and a second plate is a superimposed conducting means acting dually as a capacitor plate and field shield as more particularly described in application Ser. No. 320,394 filed Jan. 2, l973 and commonly owned by the assignee of this application.
2. Description Of The Prior Art
Many techniques have been advanced for causing by-pass connections to be established automatically around defective bit cells during normal operation of the memory system or automatically performing some equivalent corrective operation without interrupting the fixed memory circuit. One such technique provides a means for storing the address in an auxiliary memory location within a section of the defective memory location provided room or space is available therein. In this technique the defective memory location is tagged and when the latter is read out the computer which employs such a defective memory location can immediately go to the address, stored in the memory, to bring forth a corrected word from an auxiliary memory.
Another procedure embodies dividing each word line of a bulk memory into a large number of subword cells for replacement purposes and employing a memory for registering the location of the defective word cell groups in the bulk memory as well as for registering the location of alternative subword cell groups in the replacement memory in this way compensating for all bad bits expected to occur in the bulk memory by providing a replacement memory which has a bit storage capacity equal to the expected number of bad bits.
Similarly an indirect memory addressing means may be used through the use of large read only memory in which there is one bit word for each main memory word.
U.S. Pat. No. 3,753,244 relating to yield enhancement redundancy discloses a memory storage system utilizing a plurality of storage devices each of which contains redundancy and each of which is functionally organized for example on a single semiconductor chip with its own decoders. This redundancy in each device is provided by placing an extra line of cells on the chip together with a defective address store and a comparator circuit for disabling a defective line of cells and replacing it with the extra line of cells.
United States pending patent application Ser. No. 320,394, Garnache et al, filed Jan. 2, 1973 now U.S. Pat. No. 3,841,926 and Smith, U.S. Pat. No. 3,811,076 owned by this common assignee disclose an integrated circuit process and structure wherein very precise alignment tolerances may be achieved with an essentially planar structure without using a self-aligned gate process and wherein the instant invention is applicable.
In order to meet the demands of large capacity memory application, memory integrated circuits must be highly dense and fabricated with ease and economy. A particular method for producing such an integrated circuit is described in aforesaid pending application and patent wherein integrated circuits of high density are fabricated in a simplified process which allows both the use of multiple conducting layers in a dielectric above a semiconductor substrate, such as a polycrystalline silicon (polysilicon) field shield and metal interconnection lines while also making provision for very precise alignment of subsequent layers to diffusions. A doped oxide containing a suitable dopant, such as arsenic in the case of a p-type silicon substrate, is deposited on the substrate. A pattern corresponding to the desired diffusions is generated by normal photolithographic and etching techniques. A second, undoped oxide layer is thermally grown over the semiconductor substrate and the remaining doped oxide, with dopant from doped oxide simultaneously diffusing into areas of the substrate underlying the doped oxide. The undoped oxide serves to prevent autodoping. Thermally growing the undoped oxide layer converts a layer of the semiconductor surface not covered by doped oxide to the undoped oxide. Both oxide layers are then removed, leaving slight steps at the surface of the semiconductor substrate around the diffusion. The slight steps serve to allow very precise alignment of masks for subsequent process steps. Otherwise, the structure produced is very planar. An insulating layer, desirably a composite of silicon dioxide and silicon nitride in the case of a silicon substrate, is then formed on the substrate, followed by a layer of polycrystalline semiconductor, desirably doped to provide high conductivity. Openings are then etched in the polycrystalline semiconductor layer to allow formation of gate electrodes of FET's contact to the substrate, and contact of a subsequent interconnection metallization to diffusions in some of the circuits. A second insulating layer, such as silicon dioxide, is then grown on the polycrystalline semiconductor layer. Contact holes are then made to diffusions in the substrate, the substrate itself, and the polycrystalline silicon. The deposition and etching of an interconnection layer on the second insulating layer completes fabrication of the integrated circuit.
Monolithic integrated semiconductor structures having a plurality of functionally isolated individual cells that are electrically connected to provide a memory array have been described in U.S. Pat. No. 3,508,209 to B. Agusta et al and U.S. Pat. No. 3,222,653 shows a means for storing the address of an auxiliary memory location within a section of the defective memory location itself. The defective memory location is tagged and when the latter is read out, the computer which employs such a defective memory can immediately go the address, stored in the memory, to bring a corrected word from an auxiliary memory.
Arrangements for storing information which identifies bad and spare lines is known. One method embodies personalizing a semiconductor chip after final metallization by providing metal bridges which are selectively removed for example by selective etching techniques.
Semiconductor structures consists of semiconductor body and semiconductor devices formed in said body. A lead structure is formed on the body and makes contact with the devices formed in the body. After formation of active devices in a semiconductor structure and the provision of interconnection metal pads environmental protection or passivation is provided by an overlay film of glass through which conventional via holes are formed for interconnection to previously formed metal pads through and into which interconnection metal is deposited using a conventional mask to form pad limiting metallurgy.